Bumping ＆ WLP

Through the Bumping and RDL technology of Wafer Level Packaging, the I/O re-layout and solder / copper pillar bumps on the surface of the wafer are used to realize the bump processing of Flip-Chip, which further realizes the advanced Fine-Pitch Flip-Chip packaging. 

WLP (Wafer Level PKG) technology is realized by Fan-In/Fan-Out technology to the inside or outside of the chip, and 2D/2.5D/3D advanced Wafer Level Packaging technology is realized by double-sided Fan-Out and TSV silicon perforation technology.

Baseband, Bluetooth, Wifi, AI, AP, GPU/CPU and other HPC, widely used in Mobile Terminal, Smart TV, Notebook, Network, Server

1. RDL / Solder bump/Copper pillar bump

2. WLCSP (Fan-In)

3. 8~12inch wafer

4. Wafer CP

5. Fan-Out WLP (2023~2024)